The present invention relates to an embedded dynamic random access memory (eDRAM) structure employing a polycrystalline semiconductor layer to provide enhanced capacitance and methods of manufacturing the same.
Embedded dynamic random access memory (eDRAM) is a dynamic random access memory (DRAM) embedded in a logic circuit to function as a high density cache memory. The eDRAM provides comparable access time as static random access memory (SRAM) at a smaller device area per cell. Typically, eDRAM arrays are employed as an L2 level cache or L3 level cache in a processor to provide a high density memory in a processor core. Due to high performance and a compact size, eDRAM has become one of the most efficient means for continued performance of semiconductor logic circuits requiring embedded memory including processors and system-on-chip (SoC) devices.
With the scaling of semiconductor devices, more eDRAM devices are formed per unit area in a semiconductor chip. Because each eDRAM requires a capacitor to store electrical charges, available device area per capacitor decreases in each generation. Typically, the capacitor for an eDRAM requires a minimum capacitance of 10 fF to 40 fF in order to provide sufficient retention time and addressability. In the case of an eDRAM employing a deep trench capacitor, the minimum capacitance requirement poses a significant challenge. Specifically, because the capacitance of a deep trench capacitor is proportional to the surface area of a node dielectric, and the allocated device area per deep trench continues to shrink in each technology generation, the capacitance of the deep trench capacitor employing the same geometry as in the previous generation provides lesser capacitance upon device scaling. Further, there is a limit to increasing the depth of a deep trench because the etching process for formation of the deep trench becomes exponentially ineffective with increasing depth. Nonetheless, device performance of an eDRAM suffers significantly if the capacitance of an eDRAM is less than the minimum capacitance required for optimal performance of the eDRAM.